CVE-2025-45006 Information
Jul 02, 2025
cve
Description
Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints enabling potential physical memory access attacks.
Reference
https://github.com/chipsalliance/rocket-chip.git https://github.com/heyfenny/Vulnerability_disclosure/blob/main/RISCV/Rocket-chip/CVE-2025-45006/details.md https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications#ISA-Specifications
Related CNNVD
CNNVD-202507-088 (Published: 2025-07-01)
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